1. Field of the Invention
The present invention relates to electronics, and, in particular, to drivers for liquid crystal displays and the like.
2. Description of the Related Art
Liquid crystal displays (LCDs) are a dominant display technology. Depending on the particular application, in an LCD, an image is formed from anywhere from a few up to many thousands of LCD elements on a display screen. In a conventional two-dimensional LCD display having rows and columns of LCD elements (i.e., pixels), each different row and column of LCD elements is driven by an amplifier, such as a Class B amplifier. A Class B amplifier is an amplifier that has a 180-degree conduction angle.
FIG. 1 shows a schematic diagram of a conventional Class B amplifier 100 configured as a comparator-based LCD display driver to drive an LCD element, which is depicted in FIG. 1 as a capacitor 102. In one conventional type of LCD technology, if the voltage stored in capacitor 102 is greater than a certain level, then the corresponding LCD element is on; otherwise, the corresponding LCD element is off. Other LCD technologies include multiple gray-scale and/or color pixels. Depending on the particular implementation, capacitor 102 may represent the total capacitance of one or more LCD elements, such as an entire row or column of LCD elements in a two-dimensional LCD display.
In particular, amplifier 100 includes comparators (e.g., operational amplifiers (op-amps)) A1 and A2, n-type metal-oxide semiconductor field-effect transistor (MOSFET) Q1, p-type MOSFET Q2, and inverter I1. A channel node of each of transistors Q1 and Q2 is connected to driver output node NOUT. An input signal VIN is applied via driver input node NIN to the positive input of op-amp A1 and to the negative input of op-amp A2. Output signal VOUT is applied via output node NOUT to one side of capacitor 102, whose other side is connected to reference voltage VSS (e.g., ground). As such, output signal VOUT corresponds to the net charge stored in capacitor 102. Output signal VOUT is also applied as a feedback signal to the negative input of op-amp A1 and to the positive input of op-amp A2.
If the voltage level of input signal VIN is greater than the voltage level of output signal VOUT, then op-amp A1 generates a high output signal and op-amp A2 generates a low output signal. The high output signal from op-amp A1 is inverted by inverter I1 into a low signal, which is applied to the gate of N-MOSFET Q1, which is therefore off. The low output signal from op-amp A2 is applied to the gate of P-MOSFET Q2, which is therefore on. Turning on Q2 applies power supply VDD to node OUT, thereby charging capacitor 102 (assuming that VDD is greater than VOUT).
If the voltage level of input signal VIN is less than the voltage level of output signal VOUT, then op-amp A1 generates a low output signal and op-amp A2 generates a high output signal. The high output signal from op-amp A2 is applied to the gate of P-MOSFET Q2, which is therefore off. The low output signal from op-amp A1 is inverted by inverter I1 into a high signal, which is applied to the gate of N-MOSFET Q1, which is therefore on. Turning on Q1 applies reference voltage VSS to node NOUT, thereby discharging capacitor 102 (assuming that VSS is less than VOUT).
In this way, amplifier 100 functions as an LCD display driver that tends to control the charge stored in capacitor 102 such that the output voltage level VOUT is driven towards VDD or VSS depending on the level of input signal VIN. In certain technologies, the LCD element corresponding to capacitor 102 is turned on by driving input node NIN with a high input signal VIN (e.g., 1 volt), and the LCD element is turned off by driving input node NIN with a low input signal VIN (e.g., 0 volts).
In order to save power, amplifier 100 can be designed such that the differential common-mode output voltage of op-amp A1 is lower than the logic threshold of inverter I1 (i.e., the input voltage level at which the output of the inverter switches from low to high and vice versa). As such, if the output voltage level VOUT is close to the input voltage level VIN, then both Q1 and Q2 will be off, thereby saving power.
Unfortunately, this difference between the differential common-mode voltage and the inverter logic threshold reduces symmetry of the output driver. Reducing driver symmetry can lead to kinks in the DC transfer function and possible reduction of common-mode range. These problems can worsen when the operational amplifiers have lower gains. The common-mode offset between op-amp A1 and inverter I1 cuts into the accuracy of the driver by inducing an offset between the input voltage VIN and the final output voltage VOUT.
As described above, if VOUT is higher than VIN, then the output of A1 is low and therefore the output of I1 is high, which turns on Q1 and discharges capacitor 102, thereby lowering VOUT. In order to shut off Q1, VOUT must go below the logic threshold of I1. If A1 has unity gain, the static offset on VOUT will be equal to the difference in the common-mode output of A1 and the logic threshold of I1. As the gain of A1 drops, the problems worsen.
Conventional amplifiers, such as amplifier 100 of FIG. 1, can be designed to strike a balance between the competing goals of saving power and providing high driver symmetry, by designing the differential common-mode voltage to be slightly below the inverter's logic threshold. An exemplary conventional Class B amplifier for an LCD display is described by Pang-Cheng Yu and Jiin-Chuan Wu, “A Class-B Output Buffer for Flat-Panel-Display Column Driver,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 1, January 1999, the teachings of which are incorporated herein by reference. In this LCD display driver, an inverter analogous to inverter I1 of FIG. 1 has a logic threshold of 4.06 V, while the common-mode output of a comparator analogous to op-amp A1 of FIG. 1 is 0.35-0.41 V lower that the inverter's logic threshold.
Unfortunately, if the op-amp's differential common-mode voltage is too close to the inverter's logic threshold, then amplifier 100 can experience undesirable levels of overshoot and ringing. FIG. 2 shows the transfer characteristics of amplifier 100 of FIG. 1, if the op-amp's differential common-mode voltage is too close to the logic threshold of the inverter. In an exemplary amplifier implemented using a typical 0.35-micron CMOS technology, input signal VIN rises linearly from 0 volts (at time 0 nsec) to 1 volt (at time 100 nsec), stays at 1 volt until time 200 nsec, falls linearly from 1 volt back to 0 volts (at time 300 nsec), and stays at 0 volts until time 900 nsec.
As shown in FIG. 2, the resulting output signal VOUT experiences overshoot and ringing at the 1-volt level following time 100 nsec and again at the 0-volt level following time 300 nsec. For the amplifier represented in FIG. 2, there is approximately 2.5% overshoot. This overshoot and ringing (i.e., chattering) can adversely affect the operations of the display driver by causing higher power consumption associated with Q1 and Q2 being repeatedly turned on and off as the output signal rings. Chattering can also result in flickering of the LCD display.